Menlo Park, CA, United States of America

Steven Towie

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Steven Towie. Retrieved from https://idiyas.com/inventor/steven-towie

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 20(Granted Patents)


Company Filing History:


Years Active: 1999

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1 patent (USPTO):Explore Patents

Title: The Innovative Contributions of Steven Towie

Introduction

Steven Towie is a notable inventor based in Menlo Park, California. He has made significant contributions to the field of materials science, particularly in the development of barrier layers for low k materials. His work is essential in addressing corrosion issues in metal layers during processing sequences.

Latest Patents

Steven Towie holds a patent for a unique .alpha.-C:N:H/.alpha.-C:N.sub.x film liner/barrier. This invention serves as a liner and/or barrier layer that encapsulates low k materials, acting as a diffusion barrier between these materials and surrounding metal layers. As processing temperatures increase, this barrier effectively reduces the diffusion of fluorine from the low k material into the metal layers, thereby mitigating potential corrosion problems.

Career Highlights

Steven Towie is currently employed at Intel Corporation, where he continues to innovate and contribute to advancements in semiconductor technology. His expertise in materials science has positioned him as a valuable asset to the company.

Collaborations

Steven has collaborated with esteemed colleagues, including Lawrence D Wong and Indrajit Banerjee. Their combined efforts in research and development have furthered the understanding and application of barrier technologies in the industry.

Conclusion

Steven Towie's innovative work in developing barrier layers for low k materials showcases his commitment to advancing technology in the semiconductor field. His contributions are vital for improving the reliability and performance of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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