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For the Inventor, By the Inventor

Itami, Japan

Souichi Kobayashi

This inventor holds 9 USPTO granted patents. Top assignee: Mitsubishi Denki Kabushiki Kaisha. Active years: 1990-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Souichi Kobayashi. Retrieved from https://idiyas.com/inventor/souichi-kobayashi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 5

Forward Citations = 241(Granted Patents)


Location History:

  • Hyogo, JP (1991)
  • Itami, JP (1990 - 1999)
  • Tokyo, JP (1999)

Company Filing History:

goldMedal9 out of 21,351 
 
Mitsubishi Denki Kabushiki Kaisha
 patents

Years Active: 1990-1999

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9 patents (USPTO):Explore Patents
1. 5987585 - One-chip microprocessor with error detection on the chip (1999-11-16),
2. 5936455 - MOS integrated circuit with low power consumption (1999-08-10),
3. 5889429 - Semiconductor integrated circuit and semiconductor integrated circuit (1999-03-30),
4. 5706469 - Data processing system controlling bus access to an arbitrary sized (1998-01-06),
5. 5394528 - Data processor with bus-sizing function (1995-02-28),
6. 5361338 - Pipelined system for decomposing instruction into two decoding parts and (1994-11-01),
7. 5269008 - Method and apparatus for pre-processing the source of a pop instruction (1993-12-07),
8. 5062110 - Logic circuit testing apparatus (1991-10-29),
9. 4945472 - Data processor with I/O area detection (1990-07-31),

Title: Souichi Kobayashi: Innovator in Microprocessor Technology

Introduction

Souichi Kobayashi is a prominent inventor based in Itami, Japan. He has made significant contributions to the field of microprocessor technology, holding a total of 9 patents. His work focuses on enhancing the reliability and efficiency of integrated circuits.

Latest Patents

One of his latest patents is a one-chip microprocessor with error detection on the chip. This innovative design includes a built-in cache memory unit that features parities. A cache parity generating and checking unit monitors the parity of data read from the cache memory. When a parity error is detected, it triggers an internal cache parity error signal, prompting the instruction execution unit to suspend operations. This mechanism significantly improves the reliability of the system by limiting malfunctions. Another notable patent is a MOS integrated circuit with low power consumption. This circuit includes a middle potential node and various operation circuits designed to stabilize the potential of the middle node, thereby enhancing performance and efficiency.

Career Highlights

Throughout his career, Souichi Kobayashi has worked with notable companies, including Mitsubishi Electric Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in microprocessor technology.

Collaborations

He has collaborated with esteemed colleagues such as Toshio Kishi and Yuichi Saito, contributing to advancements in the field through teamwork and shared expertise.

Conclusion

Souichi Kobayashi's contributions to microprocessor technology and integrated circuits have made a lasting impact on the industry. His innovative patents reflect his commitment to improving reliability and efficiency in electronic systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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