Mitsubishi Denki Kabushiki Kaisha

Mitsubihsi Denki Kabushiki Kaisha

Souichi Kobayashi

Toshio Kishi

Ken Sakamura

Masahito Matsuo

Yukihiko Shimazu

Yuichi Saito

Masahito Matuo

Jun-ichi Hinata

Nobuaki Motoyama

A one-chip microprocessor, in which a built-in cache memory unit 20 has parities, and a cache parity generating & checking unit 21 checks parity of data read from the built-in cache memory unit 20, and when parity error is detected, outputs an internal cache parity error signal 50 to an instruction execution unit 23. By this, the instruction execution unit 23 suspends instruction execution and outputs a processor error signal 37. Accordingly, by checking parity errors of data of built-in memory and inputted address/data, instruction execution are immediately suspended to limit malfunction at least, thereby improving reliability. And by storing kinds of bus operation and errors in a register at the time of error generation, restoring possibility of system level is improved.

One-chip microprocessor with error detection on the chip

A MOS integrated circuit comprising a middle potential node to which a middle potential is to be supplied, a first operation circuit operating between a first potential and the middle potential, a second operation circuit operating between the middle potential and a second potential, and a node stabilization circuit for stabilizing the potential of the middle potential node.

MOS integrated circuit with low power consumption

A semiconductor integrated circuit which converts power-supply voltage applied from outside into optimum voltage for operating an internal circuit at the frequency of an internal clock in response to a multiplication control signal supplied to a PLL circuit from outside to generate the internal clock for operating the internal circuit by dividing a clock supplied from outside or by judging the cycle of an internal clock generated by dividing an external clock so as to supply the optimum voltage to the internal circuit.

Semiconductor integrated circuit and semiconductor integrated circuit

A novel data processing system is disclosed. Least significant bits of an address of a to-be-accessed memory of a number corresponding to a minimum specified range of a plurality of to-be-controlled memory areas each specified in an arbitrary size in advance are masked by mask bits. The access address with a predetermined number of least significant bits thereof masked is compared with each head address of a plurality of the memory areas to be controlled. It is decided in which of the memory areas to be controlled the access address is included. The memory access is controlled by access control data set for each memory area to be controlled. Further, the plurality of memory areas to be controlled are arranged in the order of priority. The to-be-controlled memory areas of higher priority are removed from the whole of the memory areas, whereby discontinuous memory areas are treated as a single memory area to be controlled.

Data processing system controlling bus access to an arbitrary sized

A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

Data processor with bus-sizing function

A pipelined data processor decomposes an instruction into a plurality of processing units (step codes), each corresponding to an operand of the instruction. In the register direct addressing mode, where the source operand of the instruction is an immediate value and the destination operand of the instruction is a register, the data processor combines the two step codes associated with the two operands into one. Thus, the number of cycles required for processing the instruction is reduced.

Pipelined system for decomposing instruction into two decoding parts and

A data processor which includes a pipeline processing unit that processes instructions, including a POP instruction. The POP instruction includes a destination operand field and has a stack top as a source. The destination for the POP instruction can be register or a memory location. The pipeline processing unit is capable of performing pre-processing with respect to both the source and destination operands prior to execution by an execution stage of the pipeline processing unit. When the destination is a memory location, pre-processing of the destination uses information from the destination operand field. When the destination operand is a general register, steps for pre-processing of the destination are merged prior to the execution stage. Pre-processing of the source uses information from the stackpointer and is conducted prior to the execution phase in response to the decoding of the operation code field of the POP instruction.

Method and apparatus for pre-processing the source of a pop instruction

An improved apparatus for testing logic circuits by implementing scan-in/scan-out operations. The improved testing apparatus is provided with input terminals for receiving control signals and data signals, one or more shift-paths each of which is made up of shift registers and control means for enabling a bidirectional shift operation of the shift-paths and for controlling the directions in which the respective shift-paths shift logical values stored in the shift registers thereof. The control means sets the shift direction in accordance with the control signals provided from the input terminals. Thereby, if there is a failing shift register in a shift-path, the failing shift register can be located by implementing the scan-in/scan-out operation utilizing the bidirectional shift of the logical data in the shift-path.

Logic circuit testing apparatus

A device for detecting whether addresses used for accessing in a memory mapped I/O system are present in the I/O area or not is provided. The device includes a mask register for logically ANDing with an incoming address. The output of the ANDing process is exclusive-ORed with an I/O address register. When an operand fetch is made to an I/O area the fetch is suspended during execution of preceding instructions. When the instruction fetch unit seeks an I/O area address, or the address calculation unit seeks an I/O area address, or data is fetched across a boundary of the I/O area, an exception is activated.

Growing community of inventors

Itami, Japan

Souichi Kobayashi