Hsinchu, Taiwan

Sou-Chuan Chiang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sou-Chuan Chiang. Retrieved from https://idiyas.com/inventor/sou-chuan-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Sou-Chuan Chiang and Semiconductor Process Innovation.

Introduction

Sou-Chuan Chiang is an inventor based in Hsinchu, Taiwan. His patent work includes a design for a semiconductor process chamber intended to improve the distribution of heating energy during epitaxial deposition.

Latest Patents

Chiang is associated with 1 patent: “Semiconductor Process Chamber with Improved Reflector.” The invention describes a substrate-processing chamber with a substrate support and a reflector positioned above it. The reflector’s body has openings of different diameters and a flange with multiple holes. Removable support kits secure the reflector to the flange and hold it at a height designed to reduce obstruction of radiation from surrounding heating elements. A cooling plate is coupled to the flange and has an opening that accommodates the reflector body. Together, these features are intended to distribute more heating energy across the substrate support.

Career Highlights

Chiang is associated with Taiwan Semiconductor Manufacturing Company Limited. His patent reflects work on chamber components and thermal management for semiconductor manufacturing processes.

Collaborations

Chia Hung Liu and Yen Chuang are identified as Chiang’s coworkers. The available information does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Sou-Chuan Chiang’s patent addresses reflector positioning and energy distribution in an epitaxial deposition chamber, highlighting a practical approach to semiconductor process equipment design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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