This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Stmicroelectronics International N.v.. Active years: 2026.
Company Filing History:
Years Active: 2026
Title: Simone Manello - Innovator in Driver Circuit Technology.
Introduction
Simone Manello is an inventor based in Buttigliera d'Asti, Italy. He has made significant contributions to the field of electronic circuits, particularly in driver circuit technology. Although he currently holds no granted patents, his innovative ideas are reflected in his latest patent applications.
Latest Patent Applications
Simone Manello's latest patent applications include the following:
1. **HALF-BRIDGE DRIVER CIRCUIT, RELATED INTEGRATED CIRCUIT, HALF-BRIDGE CIRCUIT AND METHOD** - This application describes a half-bridge driver circuit that periodically repeats switching cycles. It involves closing a first FET via a first drive signal, detecting when the current through the first FET reaches a threshold, and then opening the first FET while closing a second FET via a second drive signal. An error amplifier generates a control voltage by comparing a feedback signal with a reference signal, while a variable current generator produces a first current based on the control voltage. The error amplifier features a proportional-integral controller and a slope compensation circuit that generates a second current as a ramp signal. The threshold is determined by subtracting the second current from the first current. Upon detecting the instant, the second current is sampled, and a signal indicative of the threshold is generated by subtracting the sampled second current from the first current.
2. **DRIVER CIRCUIT COMPRISING A POWER STAGE, RELATED HALF-BRIDGE DRIVER CIRCUIT, CONTROL CIRCUIT FOR AN ELECTRONIC CONVERTER, INTEGRATED CIRCUIT AND METHOD** - This application outlines a power stage that includes parallel FETs, including a reference FET. An input PWM signal has a defined switching period. A current sensor detects the current flowing through the power stage during the switch-on period. A first circuit generates a first PWM signal with a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal with a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to produce a comparison signal. The reference current is adjusted until the logic state of the comparison signal changes. An enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit then generates