The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Jul. 09, 2024
Stmicroelectronics International N.v., Geneva, CH;
Simone Scaduto, Mussomeli, IT;
Salvatore Tricomi, San Gregorio di Catania, IT;
Simone Manello, Buttigliera d'Asti, IT;
Francesco Giorgio, Brolo, IT;
Carmelo Alberto Santagati, Catania, IT;
Stefano Saggini, Udine, IT;
Federico Iob, Udine, IT;
Agatino Antonino Alessandro, Rho, IT;
Bruno Cavallaro, Acireale, IT;
STMicroelectronics International N.V., Geneva, CH;
Abstract
A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.