Acireale, Italy

Bruno Cavallaro

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Stmicroelectronics International N.v.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bruno Cavallaro. Retrieved from https://idiyas.com/inventor/bruno-cavallaro

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 9.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Bruno Cavallaro: Power Electronics Inventor

Introduction

Bruno Cavallaro is an inventor associated with Acireale, Italy, and STMicroelectronics International N.V. His work includes a patent concerning power-stage control and FET driver circuits.

Latest Patents

Cavallaro is credited with 1 patent. The patent, “Driver Circuit Comprising a Power Stage, Related Half-Bridge Driver Circuit, Control Circuit for an Electronic Converter, Integrated Circuit and Method,” describes a power stage with parallel FETs, including a reference FET. It uses current sensing and PWM signals to assess the reference FET’s driving and conduction losses. The circuit adjusts a reference current based on a comparison of those losses, then uses the sensed current to generate individual FET enable and drive signals.

Career Highlights

Cavallaro’s listed company affiliation is STMicroelectronics International N.V. The patent reflects work on electronic converter control, power-stage efficiency, and coordinated driving of parallel FETs.

Collaborations

His listed coworkers include Francesco Giorgio and Stefano Saggini.

Conclusion

Bruno Cavallaro’s patent focuses on controlling parallel FETs through current sensing and loss-aware PWM circuitry, contributing to power electronics and electronic converter design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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