Binyamina, Israel

Shy Shyman

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shy Shyman. Retrieved from https://idiyas.com/inventor/shy-shyman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Shy Shyman: Innovator in VLSI Design Analysis

Introduction

Shy Shyman is a notable inventor based in Binyamina, Israel. He has made significant contributions to the field of Very Large Scale Integration (VLSI) design analysis. His innovative work has led to the development of a unique patent that enhances the efficiency of circuit design analysis.

Latest Patents

Shyman holds a patent for a "Device, system and method for VLSI design analysis." This invention provides a computing platform that can identify loops in circuit designs, functionally analyze them, and extract Register-Transfer-level logical elements based on the analysis results. The technology aims to improve the design process by identifying Channel Connected Sub-Networks that form combinational loops and generating zero-delay collapsed functionality.

Career Highlights

Shy Shyman is currently employed at Intel Corporation, where he continues to innovate in the field of VLSI design. His work at Intel has allowed him to collaborate with other talented professionals in the industry, further advancing the technology.

Collaborations

Shy has worked alongside colleagues such as Alexander Novakovsky and Ziyad Hanna, contributing to various projects that push the boundaries of VLSI design.

Conclusion

Shy Shyman's contributions to VLSI design analysis exemplify the impact of innovative thinking in technology. His patent and work at Intel Corporation highlight the importance of advancements in circuit design efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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