The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7073141 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 04, 2006

Filed:

Nov. 25, 2003
Applicants:

Alexander Novakovsky, Haifa, IL;

Shy Shyman, Binyamina, IL;

Ziyad Hanna, Haifa, IL;

Inventors:

Alexander Novakovsky, Haifa, IL;

Shy Shyman, Binyamina, IL;

Ziyad Hanna, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device, system and method for analysis of Very Large Scale Integration circuit designs. A computing platform may, for example, find one or more loops in a circuit design, functionally analyze the loops, and extract one or more Register-Transfer-level logical elements in relation to the analysis result. A computing platform may, for example, identify a group of at least one Channel Connected Sub-Network that forms at least one combinational loop, generate overall zero-delay collapsed functionality on an output of said group, identify one or more functional parts that form said group, and replace the group with one or more corresponding logically equivalent Register-Transfer-level devices.


Find Patent Forward Citations

Novakovsky, Alexander. (2006). Device, system and method for vlsi design analysis (U.S. Patent No. 7073141). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7073141

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