Chilung, Taiwan

Shou-Wei Hwang


Average Co-Inventor Count = 4.6

ph-index = 4

Forward Citations = 42(Granted Patents)


Location History:

  • Chilung, TW (2002 - 2003)
  • Hsin-Chu, TW (2003)

Company Filing History:


Years Active: 2002-2003

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9 patents (USPTO):Explore Patents

Title: Innovations of Shou-Wei Hwang

Introduction

Shou-Wei Hwang is a prominent inventor based in Chilung, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 9 patents. His work primarily focuses on memory arrays and non-volatile memory systems, showcasing his expertise in complementary metal-oxide-semiconductor (CMOS) processes.

Latest Patents

One of his latest patents is titled "Memory array with salicide isolation." This invention provides a memory array fabricated by a complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate with multitudes of first isolation devices aligned in the substrate and second isolation devices aligned on the substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are placed on the second isolation devices, which have a null memory function. A conductive structure is located below the surface of the semiconductor substrate, positioned between the first isolation devices. A conductive contact is placed on the conductive structure, ensuring that the correspondence of the first isolation devices and the polysilicon lines prevents short effects.

Another notable patent is the "Method for forming embedded non-volatile memory." This method describes the formation of a non-volatile memory by dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is first formed on the substrate, followed by a photoresist layer created on the ONO layer through a bit line photo process. A bit line ion implantation process is then performed to form a plurality of bit line structures. Subsequently, a first polysilicon layer is deposited to create a plurality of word lines. The CMOS ONO layer is utilized to store charge, and the ONO layer is only touched by the photoresist layer once. This method effectively addresses leakage paths between bit lines by employing a self-aligned silicide process.

Career Highlights

Shou-Wei Hwang is currently associated with Macronix International Co., Ltd., a leading company in the semiconductor industry. His innovative work has significantly advanced the development of memory technologies, making him a key figure in his field.

Collaborations

He has collaborated with notable coworkers, including Erh-Kun Lai and Yu-Ping Huang, contributing to various projects that enhance the capabilities of semiconductor devices

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