The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2003
Filed:
Dec. 06, 2001
Tung-Cheng Kuo, I-Lan, TW;
Shou-Wei Hwang, Chilung, TW;
Chien-Hung Liu, Taipei, TW;
Shyi-Shuh Pan, Kaohsiung, TW;
Abstract
A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.