The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2003
Filed:
Nov. 23, 2001
Tung-Cheng Kuo, I-Lan, TW;
Shou-Wei Hwang, Chilung, TW;
Chien-Hung Liu, Taipei, TW;
Shyi-Shuh Pan, Kaohsiung, TW;
Abstract
A method for forming an embedded non-volatile memory is disclosed. The embedded non-volatile memory, comprises memory array and logic device area, is formed on a substrate where an oxide/nitride/oxide (ONO) layer on a memory array, a gate oxide layer on a logic device area. The method is that transistors of memory array and transistors of logic device area are formed by two separately photolithography processes. In memory array, the pitch between the poly gate electrodes is equivalent and has wider spacer width. In logic device area, the pitch between the poly gate electrodes is different and has suitable spacer width. According to above-mentioned, by using separated spacer width in memory array and logic device area can avoid the leakage path between bit line to bit line in subsequently self-aligned salicide process.