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For the Inventor, By the Inventor

San Diego, CA, United States of America

Seyhan Karakulak

This inventor holds 12 USPTO granted patents and 1 published patent application. Top assignees: Western Digital Technologies, Inc., Hgst Technologies Santa Ana, Inc., S-Tec Corporation. Active years: 2013-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Seyhan Karakulak. Retrieved from https://idiyas.com/inventor/seyhan-karakulak

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12 

% Patents Active = 100.0

Average Co-Inventor Count = 3.5

ph-index = 5

Forward Citations = 116(Granted Patents)


Company Filing History:

goldMedal9 out of 5,429 
 
Western Digital Technologies, Inc.
 patents
silverMedal2 out of 23 
 
Hgst Technologies Santa Ana, Inc.
 patents
bronzeMedal1 out of 120 
 
S-Tec Corporation
 patents

Years Active: 2013-2023

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12 patents (USPTO):Explore Patents
1. 11815996 - Method and system for identifying erased memory areas (2023-11-14),
2. 11488673 - Calibrating optimal read levels (2022-11-01),
3. 11327837 - Method and system for identifying erased memory areas (2022-05-10),
4. 10884854 - Method and system for identifying erased memory areas (2021-01-05),
5. 10566061 - Calibrating optimal read levels (2020-02-18),
6. 10387246 - Method and system for scanning for erased flash memory pages (2019-08-20),
7. 9905302 - Read level grouping algorithms for increased flash performance (2018-02-27),
8. 9720754 - Read level grouping for increased flash performance (2017-08-01),
9. 9576671 - Calibrating optimal read levels (2017-02-21),
10. 9343170 - Word-line inter-cell interference detector in flash system (2016-05-17),
11. 9117529 - Inter-cell interference algorithms for soft decoding of LDPC codes (2015-08-25),
12. 8493791 - Word-line inter-cell interference detector in flash system (2013-07-23),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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