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For the Inventor, By the Inventor

Burlingame, CA, United States of America

Sean Moran

This inventor holds 7 USPTO granted patents. Top assignee: Adeia Semiconductor Bonding Technologies Inc.. Active years: 2012-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sean Moran. Retrieved from https://idiyas.com/inventor/sean-moran

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7

% Patents Active = 71.4

Average Co-Inventor Count = 3.2

ph-index = 4

Forward Citations = 27(Granted Patents)


Location History:

  • Berlingame, CA (US) (2012)
  • Burlingame, CA (US) (2013 - 2018)

Company Filing History:

goldMedal7 out of 1,909 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents

Years Active: 2012-2018

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7 patents (USPTO):Explore Patents
1. 9917042 - 2.5D microelectronic assembly and method with circuit structure formed on carrier (2018-03-13),
2. 9666513 - Wafer-level flipped die stacks with leadframes or metal foil interconnects (2017-05-30),
3. 9490195 - Wafer-level flipped die stacks with leadframes or metal foil interconnects (2016-11-08),
4. 9349672 - Microelectronic package (2016-05-24),
5. 9282640 - Interconnection element with posts formed by plating (2016-03-08),
6. 8505199 - Method of fabricating an interconnection element having conductive posts (2013-08-13),
7. 8299626 - Microelectronic package (2012-10-30),

Title: Innovations by Sean Moran in Microelectronic Assembly

Introduction

Sean Moran is a prominent inventor based in Burlingame, California, known for his significant contributions to the field of microelectronics. With a total of seven patents to his name, he has made remarkable advancements in microelectronic assembly technologies. His work focuses on enhancing the efficiency and functionality of electronic components.

Latest Patents

Among his latest patents, Sean Moran has developed innovative technologies such as a 2.5D microelectronic assembly and a method with a circuit structure formed on a carrier. This invention features a dielectric element with multiple contacts and first traces that extend parallel to the first surface. The circuit structure comprises several dielectric layers and electrically conductive features, including bumps that connect with the dielectric element's contacts. Additionally, he has patented wafer-level flipped die stacks with leadframes or metal foil interconnects, which involve stacked encapsulated microelectronic packages designed for improved connectivity and performance.

Career Highlights

Sean Moran's career is marked by his dedication to advancing microelectronic technologies. His work at Adeia Semiconductor Bonding Technologies Inc. has positioned him as a key player in the industry. His innovative patents reflect his commitment to pushing the boundaries of what is possible in microelectronics.

Collaborations

Throughout his career, Sean has collaborated with notable professionals in the field, including Belgacem Haba and Ashok S Prab

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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