Stockport, United Kingdom

Saurabh Pandey

This inventor holds 3 USPTO granted patents and 1 EPO patent. Top assignee: Nexperia B.v.. Active years: 2019-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saurabh Pandey. Retrieved from https://idiyas.com/inventor/saurabh-pandey-9ips4td1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

 

Average Co-Inventor Count = 3.2

ph-index = 1


Location History:

  • Manchester, GB (2019)
  • Stockport, GB (2020)
  • Nijmegen, NL (2020)

Company Filing History:


Years Active: 2019-2020

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3 patents (USPTO):Explore Patents

Title: Saurabh Pandey: Innovator in Semiconductor Technology

Introduction

Saurabh Pandey is a notable inventor based in Stockport, GB. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on enhancing the performance and efficiency of semiconductor devices, particularly in automotive applications.

Latest Patents

One of Saurabh's latest patents is for a semiconductor device and method of operation for low and high threshold voltage transistors. This invention features a field effect transistor semiconductor device designed with a compact footprint, making it suitable for automotive and hot swap applications. The device comprises a plurality of field effect transistor cells, including at least one low threshold voltage transistor cell and one high threshold voltage transistor cell arranged on a substrate. This configuration allows the device to operate the high threshold voltage transistor cell during linear mode and both types of transistor cells during resistive mode operation.

Another significant patent is related to power apparatus. This invention involves circuitry designed to control current flow, particularly in a cascode arrangement. The apparatus includes a first transistor with a gate, source, channel, and drain, alongside a second transistor with a stacked source, channel, and drain. A conductive clip plate connects the drain of the second transistor to the source of the first transistor, while another conductor connects the source of the second transistor to the gate of the first transistor. This innovative structure enables the second transistor to control the first transistor's state, providing efficient power management.

Career Highlights

Saurabh Pandey is currently employed at Nexperia B.V., where he continues to develop cutting-edge semiconductor technologies. His expertise in the field has positioned him as a valuable asset to the company, contributing to advancements in electronic components.

Collaborations

Saurabh has collaborated with notable colleagues, including Adam Richard Brown and Jim Brett Parkin. These partnerships have fostered a creative environment that encourages innovation and the development of new technologies.

Conclusion

Saurabh Pandey's contributions to semiconductor technology are noteworthy, with multiple patents that enhance the functionality and efficiency of electronic devices. His work at Nexperia B.V. and collaborations with esteemed colleagues further solidify his reputation as a leading inventor in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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