Sunnyvale, CA, United States of America

Sarang Agrawal

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sarang Agrawal. Retrieved from https://idiyas.com/inventor/sarang-agrawal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Sarang Agrawal: Inventor in Memory Circuit Design.

Introduction

Sarang Agrawal is an inventor based in Sunnyvale, California, and works at Intel Corporation. His patent work includes a circuit design for non-volatile memory architectures.

Latest Patents

Agrawal is associated with one patent: “Half Latch Level Shifting Circuit for Non-Volatile Memory Architectures.” The invention describes a memory device in which a level shifter drives multiple half-latch circuits. Each circuit uses a p-channel transistor, inverter stages, and an n-channel transistor connected to a bias voltage. Together, these components support level shifting and signal handling within the memory architecture.

Career Highlights

Agrawal’s listed patent reflects work on circuit techniques for non-volatile memory devices. His professional affiliation is Intel Corporation.

Collaborations

Agrawal’s listed coworker is William K. Waller.

Conclusion

Sarang Agrawal’s patent highlights his contribution to memory circuit design through a half-latch level-shifting approach for non-volatile memory architectures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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