The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jun. 02, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

William K. Waller, Boise, ID (US);

Sarang Agrawal, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/06 (2013.01); G06F 2212/2022 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory device may include a level shifter circuit that drives multiples half latch circuits. The half latch circuits may each include a p-channel transistor whose source is connected to a first voltage and whose gate is to receive addressing signals, a first inverter circuit connected between the drain of the p-channel transistor and a second voltage and whose input is connected to an output of the level shifter circuit, a second inverter circuit connected between the second voltage and a third voltage to receive an output of the first inverter circuit as input, a third inverter circuit connected between the second and third voltages to receive an output of the second inverter circuit as input, and an n-channel transistor connected between the output of the third inverter circuit and the input of the second inverter circuit, wherein a gate of the n-channel transistor is connected to a bias voltage.


Find Patent Forward Citations

Waller, William. (2026). Half latch level shifting circuit for non-volatile memory architectures (U.S. Patent No. 12645589). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12645589

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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