Santosh Subhaschandra Malagi

Title: Innovations by Santosh Subhaschandra Malagi

Introduction

Santosh Subhaschandra Malagi is a notable inventor based in Endicott, NY (US). He has made significant contributions to the field of integrated circuit (IC) design and testing. With a total of 3 patents to his name, Malagi's work focuses on enhancing the efficiency and accuracy of IC testing processes.

Latest Patents

Malagi's latest patents include innovative technologies such as "SDD ATPG using fault rules files" and "Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip." The first patent describes an integrated circuit test engine that extracts input to output propagation delays for each cell instance in an IC design. It generates cell-aware test patterns to test fabricated IC chips for defects based on fault rules files. The second patent involves a fault rules engine that generates fault rules files associated with various cell types in an IC design. This technology quantifies delays for test patterns and generates cell-aware test patterns based on extracted propagation delays.

Career Highlights

Santosh Malagi is currently employed at Cadence Design Systems, Inc., where he continues to innovate in the field of IC design and testing. His work has been instrumental in advancing testing methodologies that ensure the reliability of integrated circuits.

Collaborations

Some of his notable coworkers include Arvind Chokhani and Joseph Michael Swenton, who have collaborated with him on various projects within the company.

Conclusion

Santosh Subhaschandra Malagi's contributions to integrated circuit testing through his patents and work at Cadence Design Systems, Inc. highlight his role as a key innovator in the field. His advancements are paving the way for more efficient and reliable IC designs.