Longmont, CO, United States of America

Sandeep S Deshpande

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignee: Xilinx, Inc.. Active years: 2013-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sandeep S Deshpande. Retrieved from https://idiyas.com/inventor/sandeep-s-deshpande

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 66.7

Average Co-Inventor Count = 4.3

ph-index = 1

Forward Citations = 9(Granted Patents)


Company Filing History:


Years Active: 2013-2020

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3 patents (USPTO):Explore Patents

Title: Sandeep S Deshpande: Innovator in Circuit Design Simulation

Introduction

Sandeep S Deshpande is a notable inventor based in Longmont, Colorado, known for his contributions to circuit design simulation. He holds a total of 3 patents that showcase his innovative approaches in the field of hardware description languages.

Latest Patents

One of his latest patents is titled "Operator aware finite state machine for circuit design simulation." This invention involves simulating a circuit design specified in a hardware description language (HDL). During the simulation, a thread is initiated at the edge of a simulation clock signal to evaluate the states of a finite state machine (FSM) that represents a series of events specified in the HDL. The thread transitions from one state to the next in response to the evaluation of the current state. When a fork state is encountered, the thread is divided into two threads during the simulation, representing a composite operator in the statement. The FSM has branches from the fork state for each operand of the composite operator. Upon reaching a join state in the FSM, the two threads are merged back into one.

Another significant patent is the "Framework for reusing cores in simulation." This invention focuses on simulating a hardware description language design that includes a core and a testbench. It involves performing a first compilation of the design using a processor, generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data that describes signals crossing a compile checkpoint boundary. A subsequent compilation can then be performed by reusing the compiled core unit from the first compilation while generating a new compiled testbench using the synchronization data.

Career Highlights

Sandeep currently works at Xilinx, Inc., where he continues to develop innovative solutions in circuit design. His work has significantly impacted the efficiency and effectiveness of hardware design processes.

Collaborations

He collaborates with talented coworkers, including Valeria Mihalache and Kumar Deepak, contributing to a dynamic and innovative work environment.

Conclusion

Sandeep S Deshpande's contributions to circuit design simulation through his patents reflect his expertise and commitment to innovation in the field. His work continues to influence the development of advanced hardware design methodologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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