The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 06, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Valeria Mihalache, Los Gatos, CA (US);

Kumar Deepak, San Jose, CA (US);

Saikat Bandyopadhyay, San Jose, CA (US);

Sandeep S. Deshpande, Longmont, CO (US);

Feng Cai, Longmont, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01);
Abstract

Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.


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