The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
May. 10, 2012
Sandeep S. Deshpande, Longmont, CO (US);
Hem C. Neema, Sunnyvale, CA (US);
Valeria Mihalache, Santa Clara, CA (US);
Kumar Deepak, San Jose, CA (US);
Sonal Santan, San Jose, CA (US);
David K. Liddell, Longmont, CO (US);
Sandeep S. Deshpande, Longmont, CO (US);
Hem C. Neema, Sunnyvale, CA (US);
Valeria Mihalache, Santa Clara, CA (US);
Kumar Deepak, San Jose, CA (US);
Sonal Santan, San Jose, CA (US);
David K. Liddell, Longmont, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.