Bengaluru, India

Sakina Pitalwala

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sakina Pitalwala. Retrieved from https://idiyas.com/inventor/sakina-pitalwala

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Sakina Pitalwala: Advancing AI-Based Integrated Circuit Validation.

Introduction

Sakina Pitalwala is an inventor based in Bengaluru, India, whose patent work explores the use of artificial intelligence to validate the performance of integrated circuit features. She is associated with Intel Corporation and is identified as a woman inventor.

Latest Patents

Pitalwala is credited with 1 patent: “Enhanced Artificial Intelligence for Performance Validation of Core Integrated Circuit Features.” The invention describes systems and methods that use instruction files, trace files, performance statistics, and register-transfer-language statistics to assess integrated circuit performance. A machine-learning model predicts ratios between performance and RTL statistics, while constrained optimization uses those predictions to recommend traces for debugging.

Career Highlights

Her disclosed work applies machine learning and performance analysis to integrated circuit validation. By connecting instruction dependencies with statistical predictors and recommended debugging traces, the approach aims to help engineers investigate circuit behavior more efficiently.

Collaborations

The patent information names Kunapareddy Chiranjeevi and Karthik Varadarajan Rajagopal as coworkers associated with the work. Pitalwala’s company affiliation is Intel Corporation.

Conclusion

Sakina Pitalwala’s patent reflects an application of artificial intelligence to integrated circuit performance validation, combining machine-learning predictions with optimization to support debugging.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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