IDiyas

For the Inventor, By the Inventor

Palo Alto, CA, United States of America

Ryan N Rakvic

USPTO Granted Patents = 13

Average Co-Inventor Count = 6.0

ph-index = 5

Forward Citations = 86(Granted Patents)


Location History:

  • San Jose, CA (US) (2003)
  • Santa Clara, CA (US) (2005 - 2008)
  • Palo Alto, CA (US) (2006 - 2014)
  • Annapolis, MD (US) (2010 - 2014)

Company Filing History:

goldMedal13 out of 54,664 
 
Intel Corporation
 patents

Years Active: 2003-2014

Loading Chart...
13 patents (USPTO):
1. 8887174 - Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers (2014-11-11),
2. 8839258 - Load balancing for multi-threaded applications via asymmetric power throttling (2014-09-16),
3. 8205200 - Compiler-based scheduling optimization hints for user-level threads (2012-06-19),
4. 8108863 - Load balancing for multi-threaded applications via asymmetric power throttling (2012-01-31),
5. 8010969 - Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers (2011-08-30),
6. 7743233 - Sequencer address management (2010-06-22),
7. 7665000 - Meeting point thread characterization (2010-02-16),
8. 7424576 - Parallel cachelets (2008-09-09),
9. 7228402 - Predicate register file write by an instruction with a pending instruction having data dependency (2007-06-05),
10. 7216201 - Parallel cachelets (2007-05-08),
11. 7120749 - Cache mechanism (2006-10-10),
12. 6954848 - Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately (2005-10-11),
13. 6668306 - Non-vital loads (2003-12-23),

Title: Innovations of Ryan N Rakvic

Introduction

Ryan N Rakvic is a prominent inventor based in Palo Alto, CA. He has made significant contributions to the field of technology, particularly in software performance and multi-threaded applications. With a total of 13 patents to his name, Rakvic continues to push the boundaries of innovation.

Latest Patents

Among his latest patents is a mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers. This technique allows for the monitoring of software thread performance and the updating of software that utilizes these threads to minimize performance-inhibiting events. Another notable patent is focused on load balancing for multi-threaded applications via asymmetric power throttling. This invention determines the execution times of threads on different processing units and adjusts power settings to ensure that these threads complete execution simultaneously in future runs.

Career Highlights

Ryan N Rakvic is currently employed at Intel Corporation, where he applies his expertise in developing innovative solutions. His work has been instrumental in enhancing the efficiency of multi-threaded applications, making significant strides in the tech industry.

Collaborations

Rakvic has collaborated with notable colleagues, including Hong Wang and Richard A Hankins, contributing to various projects that aim to improve software performance and processing efficiency.

Conclusion

Ryan N Rakvic's contributions to technology through his patents and work at Intel Corporation highlight his role as a leading inventor in the field. His innovative solutions continue to shape the future of software performance and multi-threaded applications.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…