The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Apr. 05, 2005
Hong Wang, Fremont, CA (US);
Gautham N. Chinya, Hillsboro, OR (US);
Richard A. Hankins, San Jose, CA (US);
Shivnandan D. Kaushik, Portland, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
John Shen, San Jose, CA (US);
Per Hammarlund, Hillsboro, OR (US);
Xiang Zou, Beaverton, OR (US);
Jason W. Brandt, Austin, TX (US);
Prashant Sethi, Folsom, CA (US);
Douglas M. Carmean, Beaverton, OR (US);
Baiju V. Patel, Portland, OR (US);
Scott Dion Rodgers, Hillsboro, OR (US);
Ryan N. Rakvic, Palo Alto, CA (US);
John L. Reid, Portland, OR (US);
David K. Poulsen, Champaign, IL (US);
Sanjiv M. Shah, Champaign, IL (US);
James Paul Held, Portland, OR (US);
James Charles Abel, Phoenix, AZ (US);
Hong Wang, Fremont, CA (US);
Gautham N. Chinya, Hillsboro, OR (US);
Richard A. Hankins, San Jose, CA (US);
Shivnandan D. Kaushik, Portland, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
John Shen, San Jose, CA (US);
Per Hammarlund, Hillsboro, OR (US);
Xiang Zou, Beaverton, OR (US);
Jason W. Brandt, Austin, TX (US);
Prashant Sethi, Folsom, CA (US);
Douglas M. Carmean, Beaverton, OR (US);
Baiju V. Patel, Portland, OR (US);
Scott Dion Rodgers, Hillsboro, OR (US);
Ryan N. Rakvic, Palo Alto, CA (US);
John L. Reid, Portland, OR (US);
David K. Poulsen, Champaign, IL (US);
Sanjiv M. Shah, Champaign, IL (US);
James Paul Held, Portland, OR (US);
James Charles Abel, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.