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For the Inventor, By the Inventor

Sammamish, WA, United States of America

Ryan C Kinter

This inventor holds 29 USPTO granted patents and 3 published patent applications and 1 EPO patent, primarily in Multithreading Microprocessors. Top assignees: Mips Technologies, Inc., Mips Tech Limited. Active years: 2002-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ryan C Kinter. Retrieved from https://idiyas.com/inventor/ryan-c-kinter

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29 

% Patents Active = 96.6


Average Co-Inventor Count = 2.5

ph-index = 11

Forward Citations = 300(Granted Patents)


Location History:

  • Mountain View, CA (US) (2002)
  • Sunnyvale, CA (US) (2004 - 2010)
  • Los Altos, CA (US) (2008 - 2011)
  • Sammamish, WA (US) (2009 - 2012)
  • Seattle, WA (US) (2010 - 2020)

Company Filing History:

goldMedal28 out of 271 
 
Mips Technologies, Inc.
 patents
silverMedal1 out of 51 
 
Mips Tech Limited
 patents

Years Active: 2002-2020

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Areas of Expertise:
Multi-Threaded Processors
Thread Scheduler
Cache Management
Pipeline Utilization
Instruction Fetch
Coherence Domains
Scratchpad Memory
Data Cache Access
Instruction Set Processing
Memory Synchronization
Power Reduction
Translation Lookaside Buffer
29 patents (USPTO):Explore Patents
1. 10782977 - Fault detecting and fault tolerant multi-threaded processors (2020-09-22),
2. 8392663 - Coherent instruction cache utilizing cache-op execution resources (2013-03-05),
3. 8230202 - Apparatus and method for condensing trace information in a multi-processor system (2012-07-24),
4. 8151268 - Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency (2012-04-03),
5. 8131941 - Support for multiple coherence domains (2012-03-06),
6. 7925859 - Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor (2011-04-12),
7. 7873810 - Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion (2011-01-18),
8. 7853777 - Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions (2010-12-14),
9. 7769958 - Avoiding livelock using intervention messages in multiple core processors (2010-08-03),
10. 7752627 - Leaky-bucket thread scheduler in a multithreading microprocessor (2010-07-06),
11. 7739455 - Avoiding livelock using a cache manager in multiple core processors (2010-06-15),
12. 7711926 - Mapping system and method for instruction set processing (2010-05-04),
13. 7707389 - Multi-ISA instruction fetch unit for a processor, and applications thereof (2010-04-27),
14. 7681014 - Multithreading instruction scheduler employing thread group priorities (2010-03-16),
15. 7664936 - Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages (2010-02-16),

Title: Innovations in Multi-Threaded Processing: The Contributions of Ryan C Kinter

Introduction: Ryan C Kinter, based in Sammamish, WA, is a prolific inventor with an impressive portfolio of 29 patents. His work in the field of multi-threaded processors underlines crucial advancements in fault tolerance and cache coherence, emphasizing his role as a leading figure in modern computing technologies.

Latest Patents: Among his latest patents, Kinter has developed groundbreaking technologies such as "Fault Detecting and Fault Tolerant Multi-Threaded Processors." This invention describes a system where instructions from a program are executed by both a master thread and a slave thread, ensuring execution continuity even in the event of failures. If the master thread stalls, the slave thread can take over to maintain operation integrity.

Another significant patent involves the "Coherent Instruction Cache Utilizing Cache-Op Execution Resources." This innovation focuses on maintaining cache coherence across a multiprocessor system, allowing processors to efficiently manage cache maintenance operations while ensuring data integrity and execution efficiency.

Career Highlights: Kinter has made substantial contributions during his career at notable companies in the tech industry, including MIPS Technologies, Inc. and MIPS Tech Limited. His work has advanced the understanding and capabilities of modern computing systems, allowing for improved performance and reliability.

Collaborations: Throughout his journey, Kinter has collaborated with skilled professionals, including Darren Miller Jones and Sanjay Vishin. Their combined expertise has driven forward multiple innovations in the multi-threaded processor landscape, propelling advancements that have far-reaching implications in computing.

Conclusion: Ryan C Kinter's contributions to innovation in multi-threaded processing demonstrate a strong commitment to enhancing technological frameworks in computing. With his numerous patents and collaborations, Kinter epitomizes the spirit of innovation that is vital in transforming how we approach problem-solving in complex computing environments. His work will undoubtedly continue to influence the development of future technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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