The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Aug. 10, 2018
Applicant:

Mips Tech, Llc, Santa Clara, CA (US);

Inventors:

Timothy Charles Mace, Hemel Hempstead, GB;

Ryan C Kinter, Seattle, WA (US);

Assignee:

MIPS Tech, LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 11/07 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 9/30145 (2013.01); G06F 9/3814 (2013.01); G06F 9/3822 (2013.01); G06F 9/52 (2013.01); G06F 11/0754 (2013.01); G06F 9/4881 (2013.01);
Abstract

Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.


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