The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Feb. 04, 2005
Applicants:

Darren M. Jones, Los Altos, CA (US);

Ryan C. Kinter, Sammamish, WA (US);

Thomas A. Petersen, San Francisco, CA (US);

Sanjay Vishin, Sunnyvale, CA (US);

Inventors:

Darren M. Jones, Los Altos, CA (US);

Ryan C. Kinter, Sammamish, WA (US);

Thomas A. Petersen, San Francisco, CA (US);

Sanjay Vishin, Sunnyvale, CA (US);

Assignee:

MIPS Technologies, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each thread and decreases it each time the execution pipeline executes an instruction of the thread. The scheduler includes an instruction execution rate for each thread. The scheduler increases the virtual water level based on the requested rate per a predetermined number of clock cycles. The scheduler includes virtual water pressure parameters that define a set of virtual water pressure ranges over the height of the virtual water bucket. When a thread's virtual water level moves from one virtual water pressure range to the next higher range, the scheduler increases the instruction issue priority for the thread; conversely, when the level moves down, the scheduler decreases the instruction issue priority for the thread.


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