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For the Inventor, By the Inventor

San Ramon, CA, United States of America

Ruben Salvador Molina

This inventor holds 6 USPTO granted patents. Top assignees: Lsi Corporation, Lsi Logic Corporation. Active years: 2004-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ruben Salvador Molina. Retrieved from https://idiyas.com/inventor/ruben-salvador-molina

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 6

% Patents Active = 16.7

Average Co-Inventor Count = 2.4

ph-index = 2

Forward Citations = 35(Granted Patents)


Company Filing History:

goldMedal3 out of 2,353 
 
Lsi Corporation
 patents
silverMedal3 out of 3,715 
 
Lsi Logic Corporation
 patents

Years Active: 2004-2014

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6 patents (USPTO):Explore Patents
1. 8775995 - Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer (2014-07-08),
2. 8321826 - Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer (2012-11-27),
3. 7739639 - Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer (2010-06-15),
4. 7480881 - Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction (2009-01-20),
5. 7062737 - Method of automated repair of crosstalk violations and timing violations in an integrated circuit design (2006-06-13),
6. 6835972 - Bowtie and T-shaped structures of L-shaped mesh implementation (2004-12-28),

Title: Innovations of Ruben Salvador Molina

Introduction

Ruben Salvador Molina is an accomplished inventor based in San Ramon, CA (US). He holds a total of 6 patents that showcase his expertise in the field of chip-level integration processes. His innovative contributions have significantly impacted the performance and efficiency of core logic in various applications.

Latest Patents

One of his latest patents is titled "Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer." This invention discloses a method and apparatus for generating a core timing model of core logic that is accurately transferable to any chip-level integration process. The method aims to reduce performance degradation and variation caused by interactions between core logic components and chip-level components. Additionally, the core timing model is generated by filling un-wired tracks with metal in the outermost layer of the core logic after routing, and constructing a layer adjacent to this outermost layer with grounded metal that is orthogonal to the metal used in the outermost layer.

Career Highlights

Ruben has worked with notable companies such as LSI Logic Corporation and LSI Corporation. His experience in these organizations has allowed him to refine his skills and contribute to significant advancements in technology.

Collaborations

Some of his coworkers include Alexander Y Tetelbaum and Subodh Bhike, who have collaborated with him on various projects throughout his career.

Conclusion

Ruben Salvador Molina's innovative work in core timing prediction and chip-level integration processes has made a lasting impact in the field of technology. His contributions continue to influence advancements in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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