The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2009
Filed:
Aug. 18, 2006
Alexander Tetelbaum, Hayward, CA (US);
Ruben Molina, San Ramon, CA (US);
Subodh Bhike, Fremont, CA (US);
Alexander Tetelbaum, Hayward, CA (US);
Ruben Molina, San Ramon, CA (US);
Subodh Bhike, Fremont, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y. The path slack calculated for the setup timing check and for the hold timing check is generated as output.