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For the Inventor, By the Inventor

Los Altos, CA, United States of America

Ronald Pasqualini

USPTO Granted Patents = 29

Average Co-Inventor Count = 1.0

ph-index = 11

Forward Citations = 309(Granted Patents)


Company Filing History:

goldMedal29 out of 4,791 
 
National Semiconductor Corporation
 patents

Years Active: 1995-2011

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29 patents (USPTO):Explore Patents
1. 7996805 - Method of stitching scan flipflops together to form a scan chain with a reduced wire length (2011-08-09),
2. 7978454 - ESD structure that protects against power-on and power-off ESD event (2011-07-12),
3. 7863962 - High voltage CMOS output buffer constructed from low voltage CMOS transistors (2011-01-04),
4. 7723792 - Floating diodes (2010-05-25),
5. 7633311 - PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity (2009-12-15),
6. 7518419 - Wideband power-on reset circuit (2009-04-14),
7. 7424507 - High speed, low power, pipelined zero crossing detector that utilizes carry save adders (2008-09-09),
8. 7388414 - Wideband power-on reset circuit with glitch-free output (2008-06-17),
9. 7265599 - Flipflop that can tolerate arbitrarily slow clock edges (2007-09-04),
10. 7260808 - Method and metric for low power standard cell logic synthesis (2007-08-21),
11. 7185042 - High speed, universal polarity full adder which consumes minimal power and minimal area (2007-02-27),
12. 7109747 - Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock (2006-09-19),
13. 7098706 - High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops (2006-08-29),
14. 7042267 - Gated clock circuit with a substantially increased control signal delay (2006-05-09),
15. 7038898 - ESD protection circuit that can tolerate a negative input voltage during normal (non-ESD) operation (2006-05-02),

Title: Innovations and Contributions of Ronald Pasqualini

Introduction

Ronald Pasqualini, based in Los Altos, California, is a prolific inventor with an impressive portfolio of 29 patents. His work primarily focuses on advancements within the semiconductor industry, contributing significantly to the technology utilized in various electronic devices.

Latest Patents

Pasqualini's latest innovations include a method of stitching scan flip-flops together to form a scan chain with reduced wire length. This method optimizes the physical location of each scan flip-flop on semiconductor chips, leading to a substantial reduction in the total length of scan chain wires. As a result, it alleviates on-chip wiring congestion, minimizes flip-flop load capacitance, and lowers power dissipation. Another recent patent involves an electrostatic discharge (ESD) structure that protects NMOS/PMOS transistors connected to the pins of CMOS integrated circuits. This ESD protection circuit ensures the safety of the CMOS IC during power-on and power-off conditions, safeguarding it against potential ESD events.

Career Highlights

Pasqualini is currently associated with National Semiconductor Corporation, where he applies his extensive knowledge in semiconductor technology to push the boundaries of innovation. His contributions have played a vital role in enhancing the performance and reliability of integrated circuits.

Collaborations

Throughout his career, Ronald has collaborated with notable colleagues, including Brian C. Gaudet and Rajendran Sharma. These collaborations have not only enriched his projects but have also fostered a spirit of teamwork that drives technological advancements within the industry.

Conclusion

In summary, Ronald Pasqualini's substantial contributions to the field of semiconductor technology, particularly through his innovative patents, reflect his commitment to enhancing electronic device performance. As he continues to develop groundbreaking solutions, his work stands as a testament to the importance of innovation in the fast-evolving technology landscape.

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