The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2008
Filed:
Mar. 30, 2007
Applicant:
Ronald Pasqualini, Los Altos, CA (US);
Inventor:
Ronald Pasqualini, Los Altos, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A chip is initialized by a power-on reset circuit, after a turned-on power supply has reached a voltage level sufficient for normal chip operation. Logic gating is used to provide a glitch-free trigger signal that prevents erroneous chip re-initialization due to VDD glitches, and to provide a crystal warm-up delay that can be quickly tested without the use of dedicated I/O pins.