The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
Nov. 09, 2001
Applicant:
Ronald Pasqualini, Los Altos, CA (US);
Inventor:
Ronald Pasqualini, Los Altos, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.