Santa Clara, CA, United States of America

Roger Dwain Isaac

This inventor holds 21 USPTO granted patents, primarily in Memory Systems. Top assignees: Spansion LLC., Advanced Micro Devices Corporation, Globalfoundries Inc.. Active years: 2005-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Roger Dwain Isaac. Retrieved from https://idiyas.com/inventor/roger-dwain-isaac-dns4yx7y

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 81.0

Average Co-Inventor Count = 2.4

ph-index = 7

Forward Citations = 239(Granted Patents)


Location History:

  • Austin, TX (US) (2005 - 2010)
  • Santa Clara, CA (US) (2008 - 2014)
  • Campbell, CA (US) (2013 - 2016)

Company Filing History:


Years Active: 2005-2016

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Areas of Expertise:
Memory Buffering
Read/Write Performance
Latency Optimization
Cache Management
DRAM
Flash Memory
Prefetching
Signal Descrambling
Internal Buffers
Multi Media Card
Command Timing
Shared Cache
21 patents (USPTO):Explore Patents

Title: Roger Dwain Isaac: Innovator in Memory Buffering Systems

Introduction

Roger Dwain Isaac, based in Santa Clara, CA, is a prominent inventor with a remarkable portfolio that includes 21 patents. His innovative contributions primarily focus on enhancing performance and efficiency in memory systems.

Latest Patents

Two of Roger's latest patents illustrate his expertise in memory buffering systems. The first patent details a memory buffering system that significantly improves read/write performance while providing low latency for mobile systems. This system focuses on bus ownership arbitration through an innovative scheme specifically designed for memory elements in chain architecture. A unified host memory controller plays a crucial role in managing bus ownership for transfers to a unified memory buffer and other buffers within the chain architecture. This system has valuable applications within communication systems utilizing both chain and parallel architectures.

The second patent outlines a method for setting parameters and determining latency in a chained device system. This storage system organizes storage nodes in a daisy-chained network, where information flow to the nodes is governed by the constraints of communication buffers within those nodes. The design incorporates an upstream communication buffer in at least one storage node, allowing the system to maintain a determined maximum latency for communication between the master controller and multiple storage nodes.

Career Highlights

Roger has made significant contributions to leading technology companies, including Spansion LLC and Advanced Micro Devices Corporation. His work in these organizations has helped advance the fields of memory systems and storage technology, demonstrating a commitment to innovation and excellence.

Collaborations

Throughout his career, Roger has collaborated with talented individuals such as Stephan Rosner and Qamrul Hasan. These partnerships highlight the collaborative nature of technological advancements, as many groundbreaking innovations come from teamwork and shared expertise.

Conclusion

Roger Dwain Isaac's impressive array of patents and collaborations firmly establishes him as a notable inventor within the realm of memory systems. His dedication to improving memory buffering technologies contributes significantly to the evolution of mobile and communication systems, ensuring his legacy in the field of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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