Spansion Llc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Monterey Research, LLC

Roger Dwain Isaac

Stephan Rosner

Qamrul Hasan

Seiji Miura

Mitchell K Alsup

Jeremy Mah

James K Pickett

Kevin Michael Lepak

Michael A Filippo

Vydhyanathan Kalyanasundharam

William Alexander Hughes

Benjamin T Sander

Philip Enrique Madrid

Rama S Gopal

A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

Memory buffering system that improves read/write performance and provides low latency for mobile systems

A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.

Method for setting parameters and determining latency in a chained device system

Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.

System and method for read data buffering wherein analyzing policy determines whether to decrement or increment the count of internal or external buffers

A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer. Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller and a storage node have a determined maximum latency.

System and method for accessing memory

Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The descrambler component can determine the bit order of the data signals based on such patterns and can generate a transformation function that can facilitate rearranging data, which can be received from or sent to the memory device, into a predetermined bit order.

Signal descrambling detector

Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external communication buffer to the master controller.

System and method for read data buffering wherein an arbitration policy determines whether internal or external buffers are given preference

One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands are loaded into a mode register as a series of mode register write operations. Once the entire sequence of programming commands is loaded the NOR-type flash memory array the data in the data register is loaded into the NOR-type flash memory array. Other methods and circuits are also disclosed.

Using LPDDR1 bus as transport layer to communicate to flash

A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.

Byte mask command for memories

A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.

Fully associative banking for memory

A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.

Memory controller prioritization scheme

Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period.

Replacing reset pin in buses while guaranteeing system recovery

A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.

Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy

According to one exemplary embodiment, a RAM employing system includes a RAM and a RAM controller coupled to the RAM. The RAM employing system further includes a command queue, which is configured to receive time encoded RAM commands from the RAM controller. The RAM is configured to retrieve, decode, and execute each of the time encoded RAM commands in the command queue.

System and method for maintaining RAM command timing across phase-shifted time domains

A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candidates for replacement. Data entries which have been identified as candidates for replacement may be removed as candidates for replacement in response to detecting the data entry corresponds to data which is shared by at least two of the plurality of processing entities. The circuitry may maintain an indication as to which of the processing entities caused an initial allocation of data into the shared cache. When the circuitry detects that a particular data item is accessed by a processing entity other than a processing entity which caused an allocation of the given data item, the data item may be deemed classified as shared data.

Growing community of inventors

Santa Clara, CA, United States of America

Roger Dwain Isaac