Hazelwood, MO, United States of America

Robert W Herrick

This inventor holds 3 USPTO granted patents. Top assignees: United States of America as Represented by the Secretary of the Air Force, Mcdonnell Douglas Corporation. Active years: 1993-1997.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Robert W Herrick. Retrieved from https://idiyas.com/inventor/robert-w-herrick-46tresmu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.3

ph-index = 2

Forward Citations = 22(Granted Patents)


Location History:

  • Hazelwood, MO (US) (1993 - 1995)
  • Santa Barbara, CA (US) (1997)

Company Filing History:


Years Active: 1993-1997

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3 patents (USPTO):Explore Patents

Title: The Innovations of Robert W. Herrick

Introduction

Robert W. Herrick is a notable inventor based in Hazelwood, MO (US). He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on improving the efficiency and effectiveness of semiconductor devices.

Latest Patents

One of Herrick's latest patents is a mask design that minimizes leakage current between adjacent sections of a semiconductor device while reducing topographic variations. This innovative device features an etched diamond shape with an unetched 'moat' in its center. The design allows for various etching methods, although wet etching is preferred due to its cost-effectiveness and smooth sidewall finish. Prior designs typically employed a simple straight line (T-shape) across the device. Herrick's etching technique has broad applications in wafer fabrication for opto-electronic devices that require excellent electrical isolation. It is particularly useful in self-aligned or planarization processing steps that necessitate minimal topographic variations. The novel aspects of this design include the elimination of lines along the 011 crystallographic axis, which can cause retrograde slopes during wet etching, and the introduction of an 'island-to-fill-in' feature that minimizes the volume of absorbed resists.

Another significant patent by Herrick is a method for measuring and analyzing surface roughness on semiconductors. This method utilizes a scanning electron microscope to scan the etched facet edge, producing digital data that represents its profile. A Fourier transform of this edge profile generates various spatial frequency components, which can indicate issues such as lack of precise edge definition, poor liftoff samples, and metal grain size. The electron microscope's tilt adjustment feature can be used to magnify the profile shape in the y direction, enhancing the analysis.

Career Highlights

Throughout his career, Robert W. Herrick has worked with prominent organizations, including the United States of America as represented by the Secretary of the Air Force and McDonnell Douglas Corporation. His expertise in semiconductor technology has made him a valuable asset in these institutions.

Collaborations

Herrick has collaborated with notable individuals in his field, including Joseph L. Levy and Danny J. Krebs. Their combined efforts have contributed to advancements in semiconductor technology.

Conclusion

Robert W. Herrick's innovative work in semiconductor technology has led to significant advancements in the

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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