The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1997
Filed:
Sep. 11, 1995
Robert W Herrick, Santa Barbara, CA (US);
Abstract
A device and a method to minimize leakage current between adjacent sections of a semiconductor device, while minimizing topographic variations. The device has an etched shape of a diamond, with an unetched 'moat' in its center. While any type of etch will work, wet etching is usually used, both for its low cost and its good sidewell smoothness. Prior designs typically have a simple straight line (T-shape) across. The etching has general application to wafer fabrication of opto-electronic devices requiring good electrical isolation, and using self-aligned or planarization processing in later process step which require minimal topographic variations. More generally, the design technique can be applied to any etched semiconductor device where topographic variation needs to be minimized while using wet etching or other crystallographic etches. The novel features include the elimination of any lines along the 011 crystallographic axis (which give retrograde slopes in wet etching) and the use of an 'island-to-fill-in' feature, and minimize volume of absorbed resists.