Reinhard Meier

Title: Reinhard Meier: Inventor in Semiconductor Testing

Introduction

Reinhard Meier is an inventor based in Buxtehude, Germany. His work includes innovations in semiconductor testing, built-in self-test systems, and scan-chain test techniques. He is associated with 6 patents.

Latest Patents

Meier’s recent patent work addresses methods for making integrated-circuit testing more efficient and less dependent on external equipment.

“Deterministic logic built-in self-test stimuli generation” describes techniques for storing and using compressed restrict values for selected scan chains and flip-flops. The values can be inserted into test patterns to set particular flip-flops during specified shift cycles or to initialize them sequentially. This approach can avoid solving certain states with a linear equation system solver, including one used by an automatic test pattern generation tool.

“On-chip logic to support compressed X-masking for BIST” describes using masking information generated on the integrated circuit, such as information stored in read-only memory. The on-chip source supplies data to the X-masking logic, enabling masking independently of external data and supporting logic built-in self-test without requiring an external testing device.

Career Highlights

Meier has worked at NXP B.V. and Mentor Graphics Corporation. His patent work reflects a focus on design-for-test methods and on-chip logic that supports testing integrated circuits.

Collaborations

Meier’s listed coworkers include Michael Wittke and Steffen Scholze, reflecting professional connections in the semiconductor and electronic-design fields.

Conclusion

Reinhard Meier’s inventions focus on improving built-in self-test through deterministic test-stimulus generation and on-chip support for compressed X-masking.