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For the Inventor, By the Inventor

Milpitas, CA, United States of America

Rakesh Krishnaiyer

USPTO Granted Patents = 14

 

Average Co-Inventor Count = 4.0

ph-index = 4

Forward Citations = 63(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2004 - 2006)
  • Milpitas, CA (US) (2010 - 2024)

Company Filing History:

goldMedal14 out of 54,664 
 
Intel Corporation
 patents

Years Active: 2004-2024

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14 patents (USPTO):Explore Patents
1. 12032934 - Methods and apparatus to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write access (2024-07-09),
2. 11366647 - Automatic compiler dataflow optimization to enable pipelining of loops with local storage requirements (2022-06-21),
3. 11256489 - Nested loops reversal enhancements (2022-02-22),
4. 11106438 - Integration of automated complier dataflow optimizations (2021-08-31),
5. 10628141 - Compiler transformation with loop and data partitioning (2020-04-21),
6. 10268454 - Methods and apparatus to eliminate partial-redundant vector loads (2019-04-23),
7. 9921966 - Employing prefetch to reduce write overhead (2018-03-20),
8. 9785413 - Methods and apparatus to eliminate partial-redundant vector loads (2017-10-10),
9. 9009689 - Speculative compilation to generate advice messages (2015-04-14),
10. 8677338 - Data dependence testing for loop fusion with code replication, array contraction, and loop interchange (2014-03-18),
11. 7702856 - Dynamic prefetch distance calculation (2010-04-20),
12. 7155575 - Adaptive prefetch for irregular access patterns (2006-12-26),
13. 6880154 - Alias-free test for dynamic array structures (2005-04-12),
14. 6721943 - Compile-time memory coalescing for dynamic arrays (2004-04-13),

Title: Rakesh Krishnaiyer: Innovator in Compiler Optimization

Introduction

Rakesh Krishnaiyer is a prominent inventor based in Milpitas, CA. He has made significant contributions to the field of compiler optimization, holding a total of 14 patents. His work focuses on enhancing the efficiency of programming through innovative methods and apparatus.

Latest Patents

Rakesh's latest patents include groundbreaking technologies such as "Methods and apparatus to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write access." This patent discloses systems and articles of manufacture that facilitate automatic compiler optimization, allowing for improved handling of unaligned memory accesses. Another notable patent is "Automatic compiler dataflow optimization to enable pipelining of loops with local storage requirements." This technology detects local variables in source code and generates pipeline execution code, enhancing the performance of loops in programming.

Career Highlights

Rakesh Krishnaiyer is currently employed at Intel Corporation, where he continues to push the boundaries of compiler technology. His work has been instrumental in developing solutions that optimize data flow and improve overall system performance.

Collaborations

Throughout his career, Rakesh has collaborated with talented individuals such as Somnath Ghosh and Wei Ey Li. These collaborations have contributed to the advancement of innovative technologies in the field.

Conclusion

Rakesh Krishnaiyer's contributions to compiler optimization have established him as a key figure in the tech industry. His patents reflect a commitment to enhancing programming efficiency and performance.

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