The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

May. 09, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rakesh Krishnaiyer, Milpitas, CA (US);

Serge Preis, Novosibirsk, RU;

Hideki Ido, Sunnyvale, CA (US);

Anatoly Zvezdin, Novosibirsk, RU;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 2212/602 (2013.01); G06F 2212/621 (2013.01);
Abstract

The present application is directed to employing prefetch to reduce write overhead. A device may comprise a processor and a cache memory. The processor may determine if data to be written to the cache memory comprises multiple cache lines wherein at least one of the cache lines will be fully written. If the data comprises at least one cache line to be fully written, then the processor may perform a 'prefetch' wherein the processor may write dummy data to sections of the cache memory corresponding to the data to be written in full cache lines. The processor may then write actual data to the sections containing the dummy data without the processor first having to verify ownership of the sections. Any remaining data that will not be written in full cache lines may then be written to the cache memory utilizing a standard write transaction.


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