Raj Chandar Rasappan

Title: Raj Chandar Rasappan and FPGA-Based Chiplet Validation.

Introduction

Raj Chandar Rasappan is an inventor based in Folsom, California, and is associated with Intel Corporation. His patent work addresses post-silicon validation for multi-die systems-on-chip, with a focus on testing a graphics processor die independently from other chiplet components.

Latest Patents

Rasappan is credited with 1 patent: “FPGA Based Platform for Post-Silicon Validation of Chiplets.” The disclosed apparatus combines a circuit board, an active interposer, a graphics processor die, and a field-programmable gate array (FPGA). The graphics processor die contains resources for executing instructions in a multi-die system-on-chip but omits functionality assigned to a separate die. Configurable FPGA logic emulates that separate die’s functionality, enabling silicon validation of the graphics processor die independently of the other dies.

Career Highlights

Rasappan’s listed patent reflects work on hardware platforms for validating chiplet-based designs after silicon fabrication. By using an FPGA to emulate functionality located on another die, the approach supports testing a graphics processor die without requiring the complete multi-die system to be present.

Collaborations

Rasappan is associated with Intel Corporation. Rakesh Mehta and Hanmanthrao Patli are identified as coworkers.

Conclusion

Raj Chandar Rasappan’s patent describes an FPGA-based method for isolating and validating a graphics processor die within a multi-die system-on-chip, highlighting a practical approach to chiplet testing.