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For the Inventor, By the Inventor

Portland, OR, United States of America

Qiuyang Wu

USPTO Granted Patents = 8

Average Co-Inventor Count = 3.0

ph-index = 4

Forward Citations = 34(Granted Patents)


Company Filing History:

goldMedal8 out of 2,485 
 
Synopsys, Inc.
 patents

Years Active: 2010-2024

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8 patents (USPTO):
1. 11922106 - Memory efficient scalable distributed static timing analysis using structure based self-aligned parallel partitioning (2024-03-05),
2. 10423742 - Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts (2019-09-24),
3. 9754069 - Determining slack estimates for multiple instances of a cell in a hierarchical circuit design (2017-09-05),
4. 8701075 - Recursive hierarchical static timing analysis (2014-04-15),
5. 8473886 - Parallel parasitic processing in static timing analysis (2013-06-25),
6. 8443328 - Recursive hierarchical static timing analysis (2013-05-14),
7. 8261220 - Path preserving design partitioning with redundancy (2012-09-04),
8. 7739098 - System and method for providing distributed static timing analysis with merged results (2010-06-15),

Title: Innovations and Contributions of Inventor Qiuyang Wu

Introduction

Qiuyang Wu is a prominent inventor based in Portland, OR (US), known for his significant contributions to the field of electrical engineering. He holds a total of 8 patents, showcasing his innovative approach to circuit design and analysis. His work has had a substantial impact on the industry, particularly in the areas of timing analysis and integrated circuit design.

Latest Patents

One of Qiuyang Wu's latest patents is titled "Memory efficient scalable distributed static timing analysis using structure based self-aligned parallel partitioning." This method involves extracting information related to constraints and clock information from a circuit design file. It determines a topological cone based on the extracted information for partitioning the circuit design and performs timing analysis on the partitions based on this topological cone. The topological cone includes objects associated with the partition of the circuit design.

Another notable patent is "Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts." This method and apparatus focus on on-chip variation path-based pessimism reduction, improving the analysis of hierarchical integrated circuit designs. The method characterizes the top circuit level to produce a context function, which is then utilized by the block circuit level for evaluation.

Career Highlights

Qiuyang Wu is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to collaborate with other talented professionals in the field, further enhancing his contributions to innovative circuit design solutions.

Collaborations

Some of Qiuyang Wu's coworkers include Patrick D Fortner and Brian Clerkin. Their collaboration has fostered a creative environment that encourages the development of cutting-edge technologies in the realm of electrical engineering.

Conclusion

In summary, Qiuyang Wu is a distinguished inventor whose work has significantly advanced the field of electrical engineering. His innovative patents and contributions to Synopsys, Inc. highlight his expertise and commitment to enhancing circuit design and analysis.

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