The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Jan. 24, 2017
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Qiuyang Wu, Portland, OR (US);

Martin Ranke, Sunnyvale, CA (US);

Min Li, Fremont, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 17/504 (2013.01); G06F 2217/84 (2013.01);
Abstract

A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.


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