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For the Inventor, By the Inventor

Princeton, NJ, United States of America

Pranav N Ashar

This inventor holds 33 USPTO granted patents and 2 EPO patents, primarily in Circuit Verification. Top assignees: Nec USA, Inc., Nec Corporation, Nec Laboratories America, Inc.. Active years: 1995-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pranav N Ashar. Retrieved from https://idiyas.com/inventor/pranav-n-ashar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 33

% Patents Active = 75.8


Average Co-Inventor Count = 2.9

ph-index = 18

Forward Citations = 1,028(Granted Patents)


Location History:

  • Belle Meade, NJ (US) (2006)
  • Princeton, NJ (US) (1995 - 2008)
  • Manalapan, NJ (US) (2008)
  • Belle Mead, NJ (US) (2002 - 2020)

Company Filing History:

goldMedal10 out of 94 
 
Nec USA, Inc.
 patents
silverMedal9 out of 36,790 
 
Nec Corporation
 patents
bronzeMedal7 out of 718 
 
Nec Laboratories America, Inc.
 patents
4. 2 out of 125 
 
Nec Research Institute, Inc.
 patents
5. 2 out of 10 
 
Real Intent, Inc.
 patents
6. 1 out of 1,136 
 
Princeton University
 patents
7. 3 out of 834,708 
Other
 patents
where one patent can have more than one assignee

Years Active: 1995-2020

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Areas of Expertise:
Integrated Circuits
SAT-based BMC
Error Diagnosis
Model Checking
VLSI Design
Simulation Vector Generation
Boolean Satisfiability
Memory Modeling
Circuit Design Validation
Combinational Verification
Dynamic Clause Removal
Timing Analysis
33 patents (USPTO):Explore Patents
1. 10690722 - Methods and systems for efficient identification of glitch failures in integrated circuits (2020-06-23),
2. 9965575 - Methods and systems for correcting X-pessimism in gate-level simulation or emulation (2018-05-08),
3. 8131532 - Software verification using range analysis (2012-03-06),
4. 7742907 - Iterative abstraction using SAT-based BMC with proof analysis (2010-06-22),
5. 7711525 - Efficient approaches for bounded model checking (2010-05-04),
6. 7386818 - Efficient modeling of embedded memories in bounded memory checking (2008-06-10),
7. 7383166 - Verification of scheduling in the presence of loops using uninterpreted symbolic simulation (2008-06-03),
8. 7346486 - System and method for modeling, abstraction, and analysis of software (2008-03-18),
9. 7305637 - Efficient SAT-based unbounded symbolic model checking (2007-12-04),
10. 7203917 - Efficient distributed SAT and SAT-based distributed bounded model checking (2007-04-10),
11. 7019674 - Content-based information retrieval architecture (2006-03-28),
12. 6975976 - Property specific testbench generation framework for circuit design validation by guided simulation (2005-12-13),
13. 6874135 - Method for design validation using retiming (2005-03-29),
14. 6816827 - Verification method for combinational loop systems (2004-11-09),
15. 6816825 - Simulation vector generation from HDL descriptions for observability-enhanced statement coverage (2004-11-09),

Title: The Innovative Journey of Pranav N Ashar

Introduction: Pranav N Ashar, a distinguished inventor based in Princeton, NJ, has made significant contributions to the field of technology and innovation.

Latest Patents: Pranav N Ashar holds several patents in various technological domains, showcasing his versatility and creativity in inventing new solutions for complex problems.

Career Highlights: With a career spanning over two decades, Pranav N Ashar has worked with renowned tech companies, leading research institutions, and universities, shaping the landscape of modern innovation.

Collaborations: Throughout his career, Pranav N Ashar has collaborated with top-notch engineers, scientists, and researchers, fostering a culture of innovation and excellence in every project he undertakes.

Conclusion: Pranav N Ashar's relentless pursuit of innovation and his passion for creating groundbreaking solutions have established him as a prominent figure in the world of inventors and technology pioneers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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