The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2004
Filed:
Oct. 01, 1999
Yang Xia, Princeton, NJ (US);
Pranav N. Ashar, Princeton, NJ (US);
NEC Corporation, Tokyo, JP;
Abstract
A design verification method for verifying hardware designs utilizing combinational loop logic. A design verification system is provided wherein a model checker receives both a mathematical representation of the functionality of a design and a set of properties against which the mathematical model is to be checked. If the design contains a combinational loop wherein the output directly depends on its own output and must be logically completed within a single bus cycle, then modifications to the model are undertaken. A minimal number of flip-flops are first added to the combinational loop in order to break up the combinational dependency. All of the states of a state machine model of the design are then supplemented with a twin state which is exactly the same as the original state. If the current state is an original state then the next cycle progresses the state machine to twin state of the particular original state. If the current state is a twin state, then the state machine progresses to the next new original state. Thus, by modifying the model in a generic straightforward manner, the design containing a combinational loop can be verified with currently available verification systems without requiring any modifications to the model checker itself.