Simulation vector generation from hdl descriptions for observability-enhanced statement coverage

Abstract

A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.