This inventor holds 2 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1997-1998.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1997-1998
Title: Po-Tau Chu and Semiconductor Process Innovation.
Introduction
Po-Tau Chu is an inventor based in Hsinchu, Taiwan. His work includes semiconductor fabrication techniques focused on protecting bonding pads and reducing damage during the formation of patterned layers. He is associated with Taiwan Semiconductor Manufacturing Company Limited and holds 2 patents.
Latest Patents
Chu’s patent “Process for Bonding Pad Protection from Damage” describes depositing a dielectric protective cap on semiconductor bonding pads using plasma-enhanced chemical vapor deposition. The cap helps shield the pad surfaces from interactions with etching solutions during the opening of contact holes in the final passivation layer, reducing damage and residue that can affect manufacturing yield and device reliability.
His patent “Method for Forming Damage Free Patterned Layers Adjoining the Edges of High Step Height Apertures” presents a process for forming patterned layers around high-step apertures in integrated circuits. The method uses a blanket layer, a buffer layer that substantially planarizes it, and sequential patterning of the photoresist and blanket layers to help prevent damage at aperture edges.
Career Highlights
Chu’s patent work addresses practical challenges in semiconductor manufacturing, including bonding-pad protection and the formation of damage-free patterned layers. These techniques aim to support reliable processing of integrated circuits.
Collaborations
Chu’s listed coworkers include Sen Fu Chen and Wen-Cheng Chang. His company affiliation is Taiwan Semiconductor Manufacturing Company Limited.
Conclusion
Po-Tau Chu’s two patents describe semiconductor process innovations designed to protect sensitive surfaces and improve the reliability of integrated-circuit fabrication.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile