Starkville, MS, United States of America

Pidugu L Narayana

This inventor holds 29 USPTO granted patents, primarily in Memory Architecture. Top assignees: Cypress Semiconductor Corporation, Maple Optical Systems, Inc.. Active years: 1997-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pidugu L Narayana. Retrieved from https://idiyas.com/inventor/pidugu-l-narayana

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29

% Patents Active = 93.1

Average Co-Inventor Count = 2.4

ph-index = 8

Forward Citations = 235(Granted Patents)

Location History:

Starkville, MS (US) (1997 - 2000)
Santa Clara, CA (US) (2000 - 2002)
Sunnyvale, CA (US) (2001 - 2005)

Company Filing History:

27 out of 3,597

Cypress Semiconductor Corporation

patents

2 out of 3

Maple Optical Systems, Inc.

patents

Years Active: 1997-2005

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Areas of Expertise:

Memory Architecture

FIFO Design

Signal Generation

Data Packet Transmission

Programmable Delay

Oscillator Control

State Machine Design

Bus-Matching

Retransmit Recovery

Composite Flag Generation

High Speed FIFO

Precharge Scheme

29 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6907539 - Configurage data setup/hold timing circuit with user programmable delay (2005-06-14),

2. 6675336 - Distributed test architecture for multiport RAMs or other circuitry (2004-01-06),

3. 6628171 - Method, architecture and circuit for controlling and/or operating an oscillator (2003-09-30),

4. 6577635 - Data packet transmission scheduling (2003-06-10),

5. 6526470 - Fifo bus-sizing, bus-matching datapath architecture (2003-02-25),

6. 6489805 - Circuits, architectures, and methods for generating a periodic signal in a memory (2002-12-03),

7. 6469983 - Data packet transmission scheduling using a partitioned heap (2002-10-22),

8. 6400642 - Memory architecture (2002-06-04),

9. 6377071 - Composite flag generation for DDR FIFOs (2002-04-23),

10. 6366979 - Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO (2002-04-02),

11. 6292013 - Column redundancy scheme for bus-matching fifos (2001-09-18),

12. 6240031 - Memory architecture (2001-05-29),

13. 6177843 - Oscillator circuit controlled by programmable logic (2001-01-23),

14. 6070203 - Circuit for generating almost full and almost empty flags in response to (2000-05-30),

15. 6055177 - Memory cell (2000-04-25),

Title: Inventor Pidugu L Narayana

Introduction: Pidugu L Narayana is a renowned inventor based in Starkville, Mississippi, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Pidugu L Narayana holds several patents in various technological domains, including artificial intelligence, renewable energy, and medical devices.

Career Highlights: With a career spanning over two decades, Narayana has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have revolutionized industries.

Collaborations: Throughout his career, Pidugu L Narayana has collaborated with top scientists, engineers, and researchers to bring his innovative ideas to life. His collaborative efforts have resulted in the successful commercialization of several patented inventions.

Conclusion: Pidugu L Narayana's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of technology, inspiring future generations of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]