The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2004
Filed:
Jun. 13, 2000
Applicant:
Inventors:
Sangeeta Thakur, Sunnyvale, CA (US);
Emad Hamadeh, Santa Clara, CA (US);
Pidugu L. Narayana, Sunnyvale, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ; G11C 2/900 ;
U.S. Cl.
CPC ...
G01R 3/128 ; G11C 2/900 ;
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.
Thakur, Sangeeta. (2004). Distributed test architecture for multiport rams or other circuitry (U.S. Patent No. 6675336). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6675336
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile