Cypress Semiconductor Corporation

Maple Optical Systems, Inc.

Pidugu L Narayana

Andrew L Hawkins

Daniel Eric Cress

Sangeeta Thakur

Paul H Scott

Richard K Chou

Rakesh Mehrotra

Derrick J Savage

Makarand Dharmapurikar

Ping Wu

Roland T Knaack

Johnie Au

Emad Hamadeh

Bo B Wang

Padma S Nagarasa

Beng-Ghee Teh

An apparatus comprising a first delay circuit. The first delay circuit may be configured to present a data delayed signal having one of a plurality of delay times. The plurality of delay times may provide a user configurable setup/hold time.

Configurage data setup/hold timing circuit with user programmable delay

An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.

Distributed test architecture for multiport RAMs or other circuitry

An apparatus comprising an oscillator circuit and a logic circuit. The oscillator circuit may be configured to present an output signal having a frequency in response to (i) a reference signal, (ii) a control signal and (iii) the output signal. The logic circuit may be configured to present the control signal in response to (i) the output signal and (ii) the reference signal. In one example, the logic circuit may disable the oscillator when the output signal oscillates outside a predetermined range.

Method, architecture and circuit for controlling and/or operating an oscillator

The present invention is directed toward data packet transmission scheduling. Scheduling values, such as priority or other scheduling criteria assigned to data packets, are placed in a scheduling heap data structure. Packets percolate up through the heap by comparing their assigned values in pairs. Operations in the heap may be pipelined so as to provide for high-speed sorting. Thus, a few relatively simple operations can be performed repeatedly to quickly percolate packets up through the heap. Another aspect of the invention provides for fast traversal of the scheduling heap data structure. The hierarchical heap may include a highest level having a single position and each succeeding lower level having twice the number of positions as the preceding level. A binary number may represent each position in the heap. To traverse the heap, the relative movements necessary to move from one position to another may be determined from the binary number. This is useful to quickly and efficiently traverse the heap.

Data packet transmission scheduling

A circuit comprising (i) one or more input paths, (ii) one or more output paths, and (iii) one or more switch circuits. The switch circuits may be configured to connect one or more of said input paths to one or more of said output data in response to one or more control signals. The present invention may be used to read and/or write data in one or more modes of operation such as 9-Bit Big Endian Write, 9-bit Little Endian Write, 18-bit Big Endian Write, 18-bit Little Endian Write, a 36-bit Write, 9-Bit Big Endian Read, 9-bit Little Endian Read, 18-bit Big Endian Read, 18-bit Little Endian Read, 36-bit Read or other mode.

Fifo bus-sizing, bus-matching datapath architecture

A circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.

Circuits, architectures, and methods for generating a periodic signal in a memory

The present invention is directed toward methods and apparatus for data packet transmission scheduling using a partitioned scheduling heap data structure. The scheduling heap data structure has a plurality of levels for storing scheduling values for data packets according to their relative priorities. A highest level in the heap has a single position and each succeeding lower level has twice the number of positions as the preceding level. The data structure may be adapted to store a plurality of logical heaps within the heap data structure by assigning a highest level of each logical heap to a level in the heap data structure that is lower than the highest level. Thus, a single physical memory may be adapted to store plural logical heaps. This is useful because a single physical memory can be adapted to prioritize packets of various different transmission protocols and speeds.

Data packet transmission scheduling using a partitioned heap

An apparatus comprising a first memory, a second memory, a control circuit and a flag circuit. The first and second memories may each be configured to store data received from a first data input and present data to a first data output. The control circuit may be configured to control data stored in response to a write clock and control data presented in response to a read clock. The flag circuit may be configured to generate one or more composite flags in response to the first memory and the second memory.

Memory architecture

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second enable signal. The second circuit may be configured to generate a second flag signal in response to (i) the one or more first enable signals, (ii) the one or more first control signals, (iii) a second clock signal, and (iv) a pulse signal. The third circuit may be configured to generate the pulse signal in response to (i) a third clock signal and (ii) the one or more first flag signals.

Composite flag generation for DDR FIFOs

A memory circuit that allows for short retransmit recovery times by implementing a read cache memory in a FIFO device. A circuit comprising a memory array, a cache memory and a logic circuit. The memory array includes a read pointer, a write pointer and a plurality of memory rows. The cache memory is configured to store one or more memory data bits. The logic circuit is further configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.

Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO

A circuit and method comprising a multiplexer circuit, a select circuit and a buffer circuit. The multiplexer circuit may be configured to present a data bit in response to a first control signal. The select circuit may be configured to generate one or more first outputs in response to (i) the data bit and (ii) one or more first select signals. The buffer circuit may be configured to present one or more second outputs on a data bus in response to (i) the one or more first outputs and (ii) one or more second control signals. One of the second outputs may have a data state and the rest of the second outputs may have a high impedance state. The first and select signals may be generated by a logic circuit.

Column redundancy scheme for bus-matching fifos

An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.

Oscillator circuit controlled by programmable logic

An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.

Circuit for generating almost full and almost empty flags in response to

A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.

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Starkville, MS, United States of America

Pidugu L Narayana