This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2020.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2020
Title: The Innovations of Patrick Groeneveld
Introduction
Patrick Groeneveld is an accomplished inventor based in Saratoga, CA (US). He has made significant contributions to the field of integrated circuit design through his innovative patent. His work focuses on enhancing the efficiency and accuracy of logic synthesis processes.
Latest Patents
Patrick Groeneveld holds a patent for "Concurrent formal verification of logic synthesis." This patent describes techniques and systems that allow for concurrent formal verification of logic synthesis. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence. This innovative approach streamlines the design process and ensures higher reliability in IC designs.
Career Highlights
Patrick is currently employed at Synopsys, Inc., a leading company in electronic design automation. His role involves leveraging his expertise in logic synthesis to contribute to the development of advanced design tools. His innovative mindset and technical skills have positioned him as a valuable asset in the industry.
Collaborations
Throughout his career, Patrick has collaborated with notable colleagues, including Lisa R McIlwain and Michael S Quayle. These collaborations have fostered a creative environment that encourages the exchange of ideas and the development of cutting-edge technologies.
Conclusion
Patrick Groeneveld's contributions to the field of integrated circuit design through his patent and work at Synopsys, Inc. highlight his innovative spirit and dedication to advancing technology. His efforts in concurrent formal verification of logic synthesis are paving the way for more efficient and reliable IC designs.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
